Code Search (Find, Follow), Analysis (Metrics, Static, Dynamic, Bugs) and Change (Modernization, Migration, Generation, Optimization, Rearchitecting)

VHDL Parser (Front End)

The VHDL parser (front end) enables the construction of VHDL custom compilers, analysis tools, or source transformation tools. It is a member of SD's family of language front ends, based on first-class infrastructure (DMS) for implementing such custom tools. The VHDL front end includes:

• Lexical analysis including ASCII and ISO 8859-1
  • Conversion of literal values (numbers, escaped strings) into native values to enable easy computation over literal values
  • String literals represented internally in Unicode to support 16-bit characters
• Explicit grammar directly implements VHDL standard
  • Full VHDL parser, covering 1995, 2000, 2002 and 2008 standards
• Automatic construction of complete abstract syntax tree
  • Capture of comments and formats (shape) of literal values
  • Capture of ambiguous parses during parsing
  • Ability to parse large systems of files into same workspace, enabling interprocedural and cross-file analysis/transformation
  • Ability to parse different languages into same workspace, enabling codesign analysis/transformation
• Facilities to process syntax trees
  • Complete procedural API to visit/query/update/construct/print syntax trees
  • Source regeneration by prettyprinting and/or fidelity printing of syntax trees with comments and lexical formats
  • Automatically generated source-to-source transformation system
  • Ability to define custom attribute-grammar-based analyzers
  • Easy to write boolean simplification/processing rules using DMS's AC source-to-source transformations
  • Boolean Decision Diagrams (BDDs) for handling complex boolean symbolic operations quickly and at scale
• Available as source code to enable complete customization
  • Means to manage multiple language dialects with highly shared common core
• Robustness due to careful testing and application across many customers

Many of these facilities come as a consistent consequence of the front end being built to top of DMS.

Here are some sample tools (many offered by SD as products) built using the VHDL front end:

• Source Formatter
• Obfuscator

SD also offers:

• Verilog and SystemVerilog parser (front end)
• SystemC parser (front end)
• C++ parser (front end)
• C parser (front end)

Your organization may use DMS with the VHDL front end to implement and deploy your own custom tools. The sample tools can be obtained in source form as part of the VHDL front end for customization. Semantic Designs is also willing to build custom tools under contract.